The present invention relates to a semiconductor integrated circuit and a pattern lay-outing method for the same. Particularly, the present invention is concerned with a semiconductor integrated circuit having a dummy pattern within a chip and a pattern lay-outing method for the semiconductor integrated circuit.
A semiconductor integrated circuit is used in manufacturing a microdevice such as, for example, semiconductor device, liquid crystal display device, charge coupled device (CCD), or thin-film magnetic head.
Within the semiconductor integrated circuit is formed a dummy pattern in addition to various functional modules (e.g., memory, analog and logic modules). For example, the dummy pattern is formed to diminish concaves and convexes formed in an interlayer dielectric film (see Patent Documents 1 and 2 below) and it is formed also for improving the uniformity of a pattern share (see Patent Document 3 below).
Various functional modules and a dummy pattern are formed on the surface of a semiconductor wafer. The semiconductor wafer surface with various functional modules and a dummy pattern formed thereon is subjected to chemical mechanical polishing (CMP).
In CMP, abrasive cloth is pushed against the surface of the semiconductor wafer and the semiconductor wafer is revolved while being rotated on its own axis under the flow of slurry containing a fine powder of alumina or of SiO2 onto the surface of the semiconductor wafer. By CMP, the surface of the semiconductor wafer is polished into a flat surface. As a result, it becomes possible to use an exposure system with a shallow focal depth. Transfer of a fine pattern becomes possible with use of a projection lens having a large numerical aperture (NA).